The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. Such scaling down has also increased the complexity of IC processing and manufacturing.
For these advances to be realized, similar developments in IC processing and manufacturing are needed. For example, to enhance the imaging effect when a design pattern is transferred to a wafer, optical proximity correction (OPC) is used. The design pattern is adjusted to generate an image on the wafer with improved resolution. However, conventional OPC processes do not fully take into account the surrounding environment of layout patterns. As such, conventional OPC processes fail to fully consider potential interactive effects between nearby layout patterns. This may lead to degraded performance and possibly device failures.
Therefore, while conventional OPC processes have been generally adequate for their intended purposes, they have not been entirely satisfactory in every aspect. What is needed is an OPC process that takes into account the interaction between neighboring layout patterns.